--Archivo: sum_encauzado.vhdl
--Fecha de creacion: 22/01/2011.
--Ultima fecha de modificacion: 04/02/2011.
--Diseñador: Miguel Peña.
--Diseño: Sumador encauzado de 4 etapas.
--Proposito: Sumar de manera encauzada los 4 bits de los componentes de los vectores.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sum_encauzado is
    Port (
		A_i : in  std_logic_vector (3 downto 0);
		B_i : in  std_logic_vector (3 downto 0);
		CLK : in std_logic;
		CONTROL_i : in  std_logic;
		S_o : out  std_logic_vector (3 downto 0);
		C_o : out  std_logic;
		C_PREV_o : out std_logic
         );
end sum_encauzado;

architecture structural of sum_encauzado is

component sumador
    Port ( 
		A_i : in std_logic;
		B_i : in std_logic;
		S_o : out std_logic;
		C_o : out std_logic;
		C_i : in  std_logic
		);
end component;

component reg_1bit
	Port (
		 CLK : in  std_logic;
         I_i : in  std_logic;
         O_o : out  std_logic
		);
end component;

signal op : std_logic_vector (3 downto 0);--cable con el complento del bit
signal aux0 : std_logic_vector (2 downto 0);--cable para los C_out
signal aux1 : std_logic_vector(1 downto 0);--cable para el resultado del ultimo sumador y su acarreo
signal r : std_logic_vector(2 downto 0);--cable para conectar los resultados del sumador al registro
signal sr : std_logic_vector (26 downto 0);--cable que conecta las salidas del registro

begin

			op(0) <= B_i(0) xor CONTROL_i;
			op(1) <= B_i(1) xor CONTROL_i;
			op(2) <= B_i(2) xor CONTROL_i;
			op(3) <= B_i(3) xor CONTROL_i;

---------------------------------------------  I ETAPA  -------------------------

SUM1 : sumador port map

   ( 
	A_i => A_i(0),
	B_i => OP(0),
	S_o => R(0),
	C_o => AUX0(0),
	C_i => CONTROL_i
   );

PIPE1_REG0 : reg_1bit port map

	(
	I_i => R(0),
	O_o => SR(0),
	CLK => CLK
	);
	
PIPE1_REG1 : reg_1bit port map

	(
	I_i => AUX0(0),
	O_o => SR(1),
	CLK => CLK
	);

PIPE1_REG2 : reg_1bit port map

	(
	I_i => A_i(1),
	O_o => SR(2),
	CLK => CLK
	);
	
PIPE1_REG3 : reg_1bit port map

	(
	I_i => OP(1),
	O_o => SR(3),
	CLK => CLK
	);
	
PIPE1_REG4 : reg_1bit port map

	(
	I_i => A_i(2),
	O_o => SR(4),
	CLK => CLK
	);
	
PIPE1_REG5 : reg_1bit port map

	(
	I_i => OP(2),
	O_o => SR(5),
	CLK => CLK
	);

PIPE1_REG6 : reg_1bit port map

	(
	I_i => A_i(3),
	O_o => SR(6),
	CLK => CLK
	);
	
PIPE1_REG7 : reg_1bit port map

	(
	I_i => OP(3),
	O_o => SR(7),
	CLK => CLK
	);
---------------------------------------------  II ETAPA  -------------------------
SUM2 : sumador port map

	(
	A_i => SR(2),
	B_i => SR(3),
	C_i => SR(1),
	S_o => R(1),
	C_o => AUX0(1)
	);

PIPE2_REG0 : reg_1bit port map

	(
	I_i => SR(0),
	O_o => SR(8),
	CLK => CLK
	);
	
PIPE2_REG1 : reg_1bit port map

	(
	I_i => R(1),
	O_o => SR(9),
	CLK => CLK
	);

PIPE2_REG2 : reg_1bit port map

	(
	I_i => AUX0(1),
	O_o => SR(10),
	CLK => CLK
	);
	
PIPE2_REG3 : reg_1bit port map

	(
	I_i => SR(4),
	O_o => SR(11),
	CLK => CLK
	);
	
PIPE2_REG4 : reg_1bit port map

	(
	I_i => SR(5),
	O_o => SR(12),
	CLK => CLK
	);

PIPE2_REG5 : reg_1bit port map

	(
	I_i => SR(6),
	O_o => SR(13),
	CLK => CLK
	);
	
PIPE2_REG6 : reg_1bit port map

	(
	I_i => SR(7),
	O_o => SR(14),
	CLK => CLK
	);

---------------------------------------------  III ETAPA  -------------------------

SUM3 : sumador port map

	(
	A_i => SR(11),
	B_i => SR(12),
	C_i => SR(10),
	S_o => r(2),
	C_o => AUX0(2)
	);

PIPE3_REG0 : reg_1bit port map

	(
	I_i => SR(8),
	O_o => SR(15),
	CLK => CLK
	);
	
PIPE3_REG1 : reg_1bit port map

	(
	I_i => SR(9),
	O_o => SR(16),
	CLK => CLK
	);
	
PIPE3_REG2 : reg_1bit port map

	(
	I_i => r(2),
	O_o => SR(17),
	CLK => CLK
	);
	
PIPE3_REG3 : reg_1bit port map

	(
	I_i => AUX0(2),
	O_o => SR(18),
	CLK => CLK
	);
	
PIPE3_REG4 : reg_1bit port map

	(
	I_i => SR(13),
	O_o => SR(19),
	CLK => CLK
	);
	
PIPE3_REG5 : reg_1bit port map

	(
	I_i => SR(14),
	O_o => SR(20),
	CLK => CLK
	);
	
---------------------------------------------  IV ETAPA  -------------------------

SUM4 : sumador port map

	(
	A_i => SR(19),
	B_i => SR(20),
	C_i => SR(18),
	S_o => AUX1(0),
	C_o => AUX1(1)
	);
	
PIPE4_REG0 : reg_1bit port map
	(
	I_i => SR(15),
	O_o => SR(21),
	CLK => CLK
	);
	
PIPE4_REG1 : reg_1bit port map
	(
	I_i => SR(16),
	O_o => SR(22),
	CLK => CLK
	);
	
PIPE4_REG2 : reg_1bit port map
	(
	I_i => SR(17),
	O_o => SR(23),
	CLK => CLK
	);

PIPE4_REG3 : reg_1bit port map
	(
	I_i => AUX1(0),
	O_o => SR(24),
	CLK => CLK
	);

PIPE4_REG4 : reg_1bit port map
	(
	I_i => SR(18),
	O_o => SR(25),
	CLK => CLK
	);

PIPE4_REG5 : reg_1bit port map
	(
	I_i => AUX1(1),
	O_o => SR(26),
	CLK => CLK
	);
---------------------------------------------  SALIDAS  --------------------------

S_o(0) <= sr(21); 	
S_o(1) <= sr(22);
S_o(2) <= sr(23);
S_o(3) <= sr(24);
C_PREV_o <= sr(25);
C_o <= sr(26);

end structural;
